The inventive concepts described herein relate to a delay line, and more particularly to a delay cell and a delay line including the delay cell.
A delay line is a circuit that delays an input signal by a desired time. Generally, a delay line includes a plurality of delay cells coupled in series. However, in the process of delaying the input signal using the plurality of delay cells, a duty cycle of the input signal may be changed by the delay line. For this reason, a conventional delay line typically includes a separate duty cycle correction circuit that corrects a duty cycle of the delayed input signal. However, the use of a separate duty cycle correction circuit increases the overall size of the delay line.